1. Field of the Invention
This invention relates to a semiconductor dynamic random access memory (DRAM) and, more particularly, it relates to a circuit adapted to discriminate special function modes of a plurality of different types with which it is provided and entering the memory in a selected one them.
2. Description of the Related Art
Known specific function modes for a DRAM typically include parallel bit test modes. An 8-bit parallel test mode and a 16-bit parallel test mode are provided as standardized modes for a 4M DRAM adapted for 4M-word.times.1-bit and a 16M DRAM adapted for 16M-word.times.1-bit respectively.
The operation of entering a DRAM of the above identified category in a parallel bit test mode is normally carried out in a WCBR cycle as illustrated in the waveform in FIG. 1 of the accompanying drawings, although this technique is by no means usual for entering DRAMs of other categories. A WCBR cycle is a WE.multidot.CAS before RAS cycle where a /WE (write enable signal) and a /CAS (column address strobe signal) are made to become active before a /RAS (row address strobe signal). For a WCBR cycle, the address inputs A0 to A12 and the write data input Din of the DRAM may be held in any state whereas its data output Dout is always kept in an open state (high impedance state).
When a DRAM is provided with two or more than two special function modes, it has been a common practice to discriminate them by specifying a state for each of the address inputs in a WCBR cycle as illustrated in FIG. 2 of the accompanying drawings.
However, the latter entry method of specifying a state for each of the address inputs in a WCBR cycle can inevitably restrict the use of the former method (which may keep the address inputs in any state) to the disadvantage of the user and hence is currently not popular.
On the other hand, in a WCBR cycle which is a currently normally used for entering a DRAM in a special function mode out of a number of special function modes with which it is provided, the memory device is automatically refreshed by the internal row address counter of the DRAM. Contrary to this, with the latter entry method of specifying just a mode for each of the address inputs of a DRAM, its row address buffer needs to be operated and therefore the method is not compatible with the technique of automatic refresh using the internal address counter unless the entry circuit of the DRAM is modified to a considerable extent.
Thus, with a DRAM provided with special function modes of two or more than two different types, the conventional method of discriminating the special function modes for entering the memory device in one of them is accompanied by a problem of being not very convenient to the user.